|96 pin Euro-DIN connector at the motherboard||
Unbuffered data bus, bits 0 through 15
Unbuffered address bus, bits 1 through 23
16 MHz clock
External data transfer acknowledge. This signal is an input to the processor logic glue. Assertion delays external generation of the /DTACK signal.
Bus error signal generated whenever /AS remains low for more than about 250 us.
Input priority level lines 0 through 2.
Initiates a system reset.
A signal from the Power Manager indicated that associated circuits should tri-state their outputs and go inte idle state; /SYS.PWR is pulled high (deasserted) during sleep state.
Upper data strobe
Lower data strobe
Defines bus transfer as read or write signal
Data transfer acknowledge
Indicates that a wait state is inserted into the current memory cycle and that you can delay a CS.
Bus grant acknowledge
Valid memory access
Valid peripheral address
Function code lines 0 through 2
Provides +5V when the system is running normally and 0V when the system is in sleep mode.
Provides +5V when the system is running normally and 3.7V when the system is in sleep mode.
Источник: Technote HW12: Macintosh Portable PDS Development at Apple Technical Notes