 132 pin EDGE (AGP bus) connector at the computer motherboard |
Pin |
Name |
A1 |
+12 V dc |
A2 |
spare |
A3 |
Reserved* Ground |
A4 |
USB- |
A5 |
Ground |
A6 |
INTA# |
A7 |
RST# |
A8 |
GNT# |
A9 |
VCC 3.3 |
A10 |
ST1 |
A11 |
Reserved |
A12 |
PIPE# |
A13 |
Ground |
A14 |
Spare |
A15 |
SBA1 |
A16 |
VCC 3.3 |
A17 |
SBA3 |
A18 |
Reserved |
A19 |
Ground |
A20 |
SBA5 |
A21 |
SBA7 |
A22 |
Key |
A23 |
Key |
A24 |
Key |
A25 |
Key |
A26 |
AD30 |
A27 |
AD28 |
A28 |
VCC 3.3 |
A29 |
AD26 |
A30 |
AD24 |
A31 |
Ground |
A32 |
Reserved |
A33 |
C/BE3# |
A34 |
Vddq 3.3 |
A35 |
AD22 |
A36 |
AD20 |
A37 |
Ground |
A38 |
AD18 |
A39 |
AD16 |
A40 |
Vddq 3.3 |
A41 |
FRAME# |
A42 |
Spare |
A43 |
Ground |
A44 |
Spare |
A45 |
VCC 3.3 |
A46 |
TRDY# |
A47 |
STOP# |
A48 |
Spare |
A49 |
Ground |
A50 |
PAR |
A51 |
AD15 |
A52 |
Vddq 3.3 |
A53 |
AD13 |
A54 |
AD11 |
A55 |
Ground |
A56 |
AD9 |
A57 |
C/BE0# |
A58 |
Vddq 3.3 |
A59 |
Reserved |
A60 |
AD6 |
A61 |
Ground |
A62 |
AD4 |
A63 |
AD2 |
A64 |
Vddq 3.3 |
A65 |
AD0 |
A66 |
SMB1 |
B1 |
spare |
B2 |
+5 V dc |
B3 |
+5 V dc |
B4 |
USB+ |
B5 |
Ground |
B6 |
INTB# |
B7 |
CLK |
B8 |
REQ# |
B9 |
VCC 3.3 |
B10 |
ST0 |
B11 |
ST2 |
B12 |
RBF# |
B13 |
Ground |
B14 |
Spare |
B15 |
SBA0 |
B16 |
VCC 3.3 |
B17 |
SBA2 |
B18 |
SB_STB |
B19 |
Ground |
B20 |
SBA4 |
B21 |
SBA6 |
B22 |
Key |
B23 |
Key |
B24 |
Key |
B25 |
Key |
B26 |
AD31 |
B27 |
AD29 |
B28 |
VCC 3.3 |
B29 |
AD27 |
B30 |
AD25 |
B31 |
Ground |
B32 |
AD STB1 |
B33 |
AD23 |
B34 |
Vddq 3.3 |
B35 |
AD21 |
B36 |
AD19 |
B37 |
Ground |
B38 |
AD17 |
B39 |
C/BE2# |
B40 |
Vddq 3.3 |
B41 |
IRDY# |
B42 |
Spare |
B43 |
Ground |
B44 |
Spare |
B45 |
VCC 3.3 |
B46 |
DEVSEL# |
B47 |
Vddq
3.3 |
B48 |
PERR# |
B49 |
Ground |
B50 |
SERR# |
B51 |
C/BE1# |
B52 |
Vddq 3.3 |
B53 |
AD14 |
B54 |
AD12 |
B55 |
Ground |
B56 |
AD10 |
B57 |
AD8 |
B58 |
Vddq 3.3 |
B59 |
AD STB0 |
B60 |
AD7 |
B61 |
Ground |
B62 |
AD5 |
B63 |
AD3 |
B64 |
Vddq 3.3 |
B65 |
AD1 |
B66 |
SMB0 |
The AGP bus is based on the
PCI [Peripheral Component Interface] spec, using the PCI specification as an
operational baseline. The AGP specification adds 20 additional signals not included
in the PCI bus. The AGP specification defines the Protocol, Electrical and Mechanical
aspects of the bus.
The Mechanical definitions include a connector and Add-in card. The Card sizes
and 1.5v and 3.3v connectors are also defined with in the spec. There are five
connectors defined: AGP 3.3v, AGP 1.5v, AGP Universal, AGP Pro Universal, AGP
Pro 3.3v, and AGP Pro 1.5v. PCI and AGP boards are not mechanically interchangeable.
The AGP 1.0 specification defined 1x and 2x speeds with the 3.3v keyed connector.
The AGP 2.0 specification defined 1x, 2x and 4x speeds with the 3.3v, or 1.5v
keyed connector or a "Universal" connector which supported both card types.
The AGP Pro specification defined 1x, 2x and 4x speeds with the 3.3v, or 1.5v
keyed connector or a "Universal" connector which supported both card types.
The AGP 3.0 specification defined 1x, 2x, 4x and 8x speeds with the 1.5v keyed
connector or a 1.5v AGP Pro connector.
Each up-grade is a supper-set of the 1x mode, so 4x will also support 1x. The
base clock rate is 66MHz, but to achieve to 2x, 4x, and 8x speeds the clock
is doubled each time. AGP uses both edges of the clock to transfer data.
AGP (1x): 66MHz clock, 8 bytes/clock, Bandwidth: 266MB/s [3.3V or 1.5V signal
swing]
AGP 2x: 133MHz clock, 8 bytes/clock, Bandwidth: 533MB/s [3.3V or 1.5V signal
swing]
AGP 4x: 266MHz clock, 16 bytes/clock, Bandwidth: 1066MB/s [1.5V signal swing]
AGP 8x: 533MHz clock, 32 bytes/clock, Bandwidth: 2.1GB/s [0.8V signal swing]
The AGP data bus may be 8, 16, 24, 32, or 64 bits. Due to timing requirements
the maximum bus length is 9". The trace impedance is specified as 65 ohms
+/- 15 ohms (no termination resistor is specified). For the 8x speed the bus
requires a parallel termination. | |